module Control(
  input   [5:0] oPCode,
  
  output        regDst,
  output        branch,
  output        memRead,
  output        mem2reg,
  output        memWrite,
  output        ALUsrc,
  output        regWrite,
  output  [2:0] ALUop
);

  reg [9:0]   out;

  always @(oPCode)
    case(oPCode)
      6'b000000: out = 10'b1000001100;  //R-type
      6'b001000: out = 10'b0000011010;  //addi
      6'b001100: out = 10'b0000011000;  //andi
      6'b001101: out = 10'b0000011001;  //ori
      6'b101011: out = 10'b0000110010;  //sw
      6'b100011: out = 10'b0011011010;  //lw
      6'b000100: out = 10'b0100000011;  //beq
    endcase
    
  assign regDst =   out[9];
  assign branch =   out[8];
  assign memRead =  out[7];
  assign mem2reg =  out[6];
  assign memWrite = out[5];
  assign ALUsrc =   out[4];
  assign regWrite = out[3];
  assign ALUop =    out[2:0];

endmodule
